1. Field of the Invention
The present invention relates to a coding apparatus, a coding method, a program for executing the method, and a recording medium storing the program, the above being applicable for use in the coding of video data by means of the H.264 ISO/IEC 14496-10 AVC coding method (hereinafter referred to as AVC). More particularly, the present invention relates to configurations for arithmetic coding processing wherein the bit rate is controlled by predicting the number of generated bits from the bin size, such prediction being conducted with the use of a predictive function whose polynomial degree changes once the bin size exceeds a threshold value. The configurations of the present invention are simpler than those of the related art, and thus the scale of the circuitry involved therein and the energy-consumed thereby is reduced.
2. Description of the Related Art
Various video equipment of the related art codes video data using coding methods such as Moving Picture Experts Group Phase 2 (MPEG-2), MPEG-4, and AVC. Among such coding methods, the AVC coding method is more computationally intensive for coding and decoding than the MPEG-2 and MPEG-4 coding methods. At the same time, however, with AVC it is possible to obtain higher compression ratios compared to those of MPEG-2 and MPEG-4.
AVC includes two high-efficiency coding schemes: context-adaptive variable length coding (CAVLC) and context-adaptive binary arithmetic coding (CABAC). Syntax elements are entropy coded using one of the above two schemes. Regardless of which scheme is used, AVC is able to adaptively assign symbols according to conditions in surrounding blocks, and thus higher compression ratios can be obtained compared to those of MPEG-2 and MPEG-4. Additionally, since CABAC is an arithmetic coding process, CABAC can assign symbols more efficiently than CAVLC. Consequently, the coding efficiency (i.e., the compression ratio) can be improved by using CABAC rather than CAVLC.
FIG. 9 is a block diagram illustrating the configuration of an AVC coding apparatus of the related art. The coding apparatus 1 implements CABAC. In the coding apparatus 1, a predictive coder 2 codes input picture data D1 with the use of prediction values. Subsequently, an arithmetic coder 3 codes each syntax element using CABAC.
The input picture data D1 received as input by the predictive coder 2 has been sorted by frame according to the GOP structure, the sorting conducted by means of a sort circuit not shown in the drawings. In the predictive coder 2, a subtractor 5 first subtracts prediction values D2 from the input picture data D1, and then outputs the resulting prediction error. An orthogonal transformation unit 6 is made up of a discrete cosine transform circuit or similar circuit that applies an orthogonal transformation to the prediction error and then outputs the resulting coefficient data. The quantization scale in a quantizer 7 is switched as a result of control by a rate controller 8A provided in a controller 8. The quantizer 7 quantizes the coefficient data output from the orthogonal transformation unit 6, outputting the results as quantized data D3.
A dequantizer 9 dequantizes the data D3 output from the quantizer 7, thereby restoring the data that was input into the quantizer 7. An inverse orthogonal transformation unit 10 then applies an inverse orthogonal transformation to the data output from the dequantizer 9, thereby restoring the data that was input into the orthogonal transformation unit 6. An adder 11 adds the prediction values D2 to the data output from the inverse orthogonal transformation unit 10, thereby restoring the input picture data D1. Frame memory 12 then stores the decoded input picture data D1 as reference picture data. The predictive coder 2 subsequently performs inter-prediction, wherein motion in the reference picture data stored in the frame memory is compensated for using a motion compensator 13, thereby generating prediction values D2. The predictive coder 2 also performs intra-prediction, wherein prediction values D2 are generated using an intra-prediction unit not shown in the drawings. The predictive coder 2 then inputs the output data from the quantizer 7 into the arithmetic coder 3 along with motion vectors, prediction mode data, or other information.
In the arithmetic coder 3, a binarization unit 15 converts the many-valued syntax elements from the output data of the quantizer 7, the motion vectors, and the prediction mode data into binary values, the binarization being conducted according to rules that depend on the type of the respective syntax elements. The binarization unit 15 then outputs the resulting series of variable-length binary symbols.
A context calculation unit 16 then conducts context calculation on each bit of the binary symbols to be output from the arithmetic coder 3. The context calculation is conducted on the basis of information about surrounding data to be coded and the values of already-coded binary symbols, and solves for a probability state variable indicating the probable value of each bit in the binary symbol being processed. The context calculation unit 16 stores the probability state variables in a probability table format, for example, and probability state variables that have been solved for are issued to a binary arithmetic coder 17 by means of the probability table. In addition, upon solving for the probability state variable of a single binary symbol, the context calculation unit 16 updates the corresponding probability state variable recorded in the probability table.
Using the probability table issued from the context calculation unit 16, the binary arithmetic coder 17 codes and outputs the current binary symbols being processed. A buffer 18 stores the output data from the binary arithmetic coder 17 along with header information or similar data, and then outputs the resulting coded data D4 as part of a bitstream.
The controller 8 controls the operation of the coding apparatus 1, selecting the optimal prediction mode by which to process the input picture data D1, and issuing commands to the motion compensator 13 and intra-prediction unit for generating prediction values D2 according to the optimal prediction mode. Additionally, the controller 8 executes rate control processing by using the rate controller 8A to switch the quantization scale of the quantizer 7.
FIG. 10 is a block diagram illustrating the configuration of the coding apparatus 1 with regard to the processing of the rate controller 8A provided in the controller 8. In FIG. 10, ME is a motion vector detection (i.e., motion estimation) circuit. During the bit allocation processing in step SP1, the controller 8 distributes allocatable bits to each picture and calculates a target number of bits for the picture currently being coded. The controller 8 also calculates the target number of bits per rate control unit from the picture currently being coded. The rate control unit herein is the coding unit of the coding apparatus 1 (i.e., a macroblock).
More specifically, the controller 8 divides the target bit rate of the coded data D4 to be output from the coding apparatus 1 by the number of GOPs per unit time, thus yielding the target number of bits allocatable to a single GOP. The controller 8 may also distribute the target number of bits for a single GOP thus calculated to each picture according to a ratio defined by picture type, thereby calculating the target number of bits for the picture currently being coded. The controller 8 may also divide the target number of bits for the picture currently being coded by the number of macroblocks constituting a single picture, and thereby calculate the target number of bits for a single macroblock. The controller 8 then issues the calculated target number of bits for a single macroblock to the rate controller 8A.
When calculating the target number of bits for a coding unit-block, the controller 8 may also monitor the number of bits in the coded data D4 generated as a result of the coding processing by monitoring the amount of free space in the buffer 18. Every time the coding for a single picture is completed, the controller 8 re-calculates, from the coded data D4 of the single picture, the target number of bits allocatable to the remaining pictures that constitute the current GOP. The re-calculated target number of bits may also be distributed to each picture according to picture type, thereby calculating the target number of bits for the next picture to be coded. The controller 8 may also re-calculate the target number of bits for a single macroblock from the target number of bits of the next picture to be coded, and then issue the re-calculated target number of bits to the rate controller 8A.
During the processing by the rate controller 8A as indicated by step SP2, the controller 8 may control the quantization scale of the controller 8 using a feedback control of the rate controller 8A, such that the number of bits in the coded data D4 becomes the target number of bits calculated in step SP1. More specifically, the controller 8 outputs quantization scale data DQ that determines the quantization scale of the quantizer 7 according to the target number of bits that was issued as a result of the bit allocation processing in step SP1. In this case, the controller 8 corrects and outputs the quantization scale data DQ according to the number of bits in the coded data D4 for the preceding macroblock. More specifically, when the number of bits in the coded data D4 is large with respect to the target number of bits, the quantization scale data DQ is corrected such that the quantization step size is increased and the number of generated bits is decreased. In contrast, when the number of bits in the coded data D4 is small with respect to the target number of bits, the quantization scale data DQ is corrected such that the quantization step size is decreased and the number of generated bits is increased. In this case, the quantization scale data DQ may be corrected using the actual number of bits in the coded data D4 as detected by the binary arithmetic coder 17, rather than the number of bits in the coded data D4 found by monitoring the buffer 18.
Using an activity detector not shown in the drawings, the coding apparatus 1 analyzes the input picture data D1 and detects per-macroblock activity that indicates coding difficulty. The activity herein may be calculated as the sum of squares or the sum of the absolute values of the high-activity area in the input picture data D1, or alternatively, the sum of squares of the sum of the absolute values of the prediction error output from the subtractor 5.
During the correction processing in step SP3, the controller 8 corrects the quantization scale data DQ calculated by the rate controller 8A according to the level of activity, and then outputs the corrected quantization scale to the quantizer 7. More specifically, for the portions having high activity wherein a degraded picture would be noticeably apparent, the quantization scale data DQ is corrected such that the quantization step size is decreased. In contrast, for the portions having low activity wherein a degraded picture would not be noticeably apparent, the quantization scale data DQ is corrected such that the quantization step size is increased.
Methods have been proposed regarding AVC coding for easily detecting the number of generated code bits, this number serving as a basis for the selection of the optimal prediction mode (cf. JP-A-2005-318296 and Toshiba Review, Vol. 60, No. 1 (2005), 17-20). The technique disclosed in JP-A-2005-318296 involves detecting the number of generated code bits by summing the bin sizes of the binary symbols output from the arithmetic coder 3. The proposal disclosed in Toshiba Review involves detecting the number of generated coded bits by calculating a linear approximation using cumulative values of the bin sizes of the binary symbols. The bin size herein refers to the number of bits in a binary symbol.
The rate controller previously described with reference to FIG. 10 uses a feedback control based on the number of bits generated in the arithmetic coding processing. Consequently, real-time coding of the input picture data D1 by the coding apparatus 1 requires that the arithmetic coder 3 process binary symbols at high speeds. However, the processing conducted by the arithmetic coder 3 is very computationally intensive. Consequently, there is a problem in that if a coding apparatus 1 in accordance with the related art is to code the input picture data D1 in real-time, then the scale of circuitry involved is increased due to the increased complexity in the configuration of the arithmetic coder 3, and furthermore energy consumption is also increased.